DRAMs of the kind that use a switch in series with a capacitor for storage are among the most important of all integrated circuits. A continuing trend in DRAMs is the increase in the number of memory cells that are stored in a single chip, a number that is now in the millions and is still increasing.
It is desirable to decrease the size of individual memory cells of the array so as to increase the capacity of DRAMs while limiting the size of the semiconductor chip. A popular memory cell uses an n-channel metal oxide semiconductor transistor (MOSFET), also known as an insulated gate field effect transistor (IGFET), as the switch and a capacitor. The use of a storage capacitor that is formed as a deep vertical trench in the chip, adjacent the transistor with which it is in series, is widespread. Associated with such a trend is a trend towards the use of a vertical transistor formed at the top of the trench to increase still further the number of cells that can be formed in a single semiconductor chip.
A problem that has arisen in a memory cell that uses both a vertical trench storage capacitor and a vertical transistor is providing conveniently the necessary isolation between the storage capacitor and the transistor.